Many communications systems require stable and low noise frequency for communication. Exemplary such systems are GSM, DCS 1800 and Bluetooth. Stable frequencies, flexible to various reference oscillator frequencies, can be achieved by a fractional-N synthesizer. A fractional-N synthesizer generates frequencies between two respective nominal frequencies determined from two rationals times a reference frequency. Generally the rationals are achieved by a frequency dividing circuit altering between two integer divisors. By altering between the rationals according to a specified pattern a desired frequency can be achieved for a range of reference oscillators. A problem of altering between frequencies (division ratios) is that phase noise is introduced. The synthesized frequency will comprise a range of frequency components of the output signal being higher or lower than the desired frequency. A ΣΔ-controlled fractional synthesizer according to prior art is shown in FIG. 1.
U.K. Patent Application GB2097206 illustrates a phase locked loop type frequency synthesizer including a dual switched frequency divider. A compensation signal is generated and adaptively adjusted to reduce phase jitter. The phase jitter is due to the output pulses of the variable divider not being regularly spaced. In one embodiment the irregularities are suppressed before the signal is applied to the input of the phase comparator.
U.S. Pat. No. 5,834,987 describes frequency synthesizer systems and methods including a programmable frequency divider. The divider is controlled to divide frequency of a VCO output signal by a first or a second integral ratio. A ΣΔ modulator is responsive to a modulation input to produce the divider control input. A ripple compensation signal is provided to phase detector output.
U.S. Pat. No. 4,179,670 discloses a fractional division ratio synthesizer with jitter compensation. Jitter compensation is inserted at output of phase comparator. The compensated signal is passed through a loop filter to a voltage-controlled oscillator. A nominal division ratio of M is increased by 1 for a fraction of a number of periods at a reference frequency, fr. The fraction is a ratio of N/2n, where N may be increased by 1 on a cyclic basis using a ΣΔ modulator clocked at fr.
U.S. Pat. No. 4,771,196 describes an electronically variable active analog delay line utilizing cascaded differential transconductance amplifiers with integrating capacitors.
U.S. Patent application US20020008557 presents a digital phase locked loop where the output of a digital controlled oscillator feeds multi-stage tapped delay lines, providing a range of clock signals at different frequencies. A control signal representing timing error in the output signal determines a tap of the tapped delay line for output.
U.S. Pat. No. 5,036,294 reveals a switched capacitor phase locked loop.
None of the cited documents above discloses a method and system for frequency synthesis providing jitter compensation prior to phase detection or posterior to oscillator signal generation of a phased locked loop, wherein jitter compensation is introduced by means of a variable delay line.